AAC / CellSMART Octal (8-port) DS1 (w/CSU) Physical Layer Module
- Specifications
- Ordering Information
- Support Information
- Datasheet
| Common Requirements | |
| Fractional support | N x 64 or N x 56 |
| Framing format | ESF or SF (D4) |
| Interface connector | RJ-48C |
| Line code | B8ZS or AMI |
| Line rate, internal clock | 1.544 Mbps +/- 50 bps (1.544 Mbps +/- 130 bps when the timing is derived from the input signal). |
| Input Requirements | |
| Jitter tolerance | Conforms to TR-NWT-000499 Issue 5, Section 7.3.1, Figure 7-2 for Category II equipment |
| Line rate tolerance | 1.544 Mbps +/- 200 bps |
| Signal level | 0 to -27.5 dBm |
| Output Requirements | |
| Jitter generation | Conforms to ITU-T Recommendation G.824 (03/93), Section 2.1, Table 1 |
| Line build out | 0, -7.5 dB, -15 dB, user selectable |
| Output level | 3.0 V peak +/- 10% into 100 ohms at output connector |
| Pulse shape | Conforms to ANSI T1.403-1995, Figure 2 and TR62411, Figure 21 |
| Standards Compliance | |
| Meets applicable requirements of the following standards/generic requirements | ANSI T1.403-1995, Standard for Telecommunications, "Network-to-Customer Installation--DS1 Metallic Interface, " March 21, 1995. ANSI T1.102-1993, Standard for Telecommunications, "Digital Hierarchy--Electrical Interfaces, " December 8, 1993. ANSI T1.107-1988, Standard for Telecommunications, "Digital Hierarchy--Formats Specificiation, " August 25, 1988. ITU-T G.824-1993, "Digital Networks--The Control of Jitter and Wander within Digital Networks which are Based on the 1544 kbit/s Hierarchy, " March 1993. |