AAC / CellSMART HSSI Physical Layer Module

Common Requirements
Line rate, internal clock	1 Mbps to 51.2 Mpbs, user selectable for input and output rates
Maximum common mode input voltage	-2.85 V to -0.8V
Maximum differential input voltage	1.5 V

Balanced Signals
DC line offset	100 mV max
Input sensitivity	< 150 mV
Line impedance	110 ohms
Output short circuit current	<= 50 mA
Output voltage V_o	0.59 V_pp < V_o < 1.5 V_pp
Rise time & fall time	0.5 ns <= t <= 2.3 ns

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